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| gm/ID Design Methodology for CMOS Analog Low Power Integrated Circuits |
| 価格 ：\15,083（税込） |
Table of Contents:
Chapter 1: Synthesis of the Intrinsic Gain Stage. Introduction/ Chapter 2: The Charge Sheet Model revisited/ Chapter 3: A graphical representation of the current in MOS transistors/ Chapter 4: The E.K.V. - A.C.M. model. - preliminary/ Chapter 5:Small signal parameters/ Chapter 6: Real transistors. Output conductance. Short channel effects. Models or Tables? gm/ID synthesis using tables is feasible. Synthesis of the Intrinsic Gain Stage/ Chapter 7: Synthesis of Miller Op Amps.(emphasis on low-voltage, low-power)/ Chapter 8: Synthesis of cascode Op Amps. (emphasis on low-voltage, low-power) |
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ISBN13 ： 978-0-387-47100-6 |
| 著者 |
Paul G.A. Jespers |
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Springer |
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| gm/ID Design Methodology for CMOS Analog Low Power Integrated Circuits |
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